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W39V080A data sheet 1m 8 cmos flash memory with lpc interface publication release date: dec. 28, 2005 - 1 - revision a4 table of contents- 1. general description ......................................................................................................... 3 2. features ................................................................................................................................. 3 3. pin configurations ............................................................................................................ 4 4. block diagram ...................................................................................................................... 4 5. pin description ..................................................................................................................... 4 6. functional description ................................................................................................... 5 6.1 interface mode selection and description ...................................................................... 5 6.2 read (write) mode ......................................................................................................... 5 6.3 reset operation .............................................................................................................. 5 6.4 boot block operation and hardware protection at initial- #tbl & #wp ........................ 5 6.5 sector erase command ................................................................................................. 6 6.6 program operation ......................................................................................................... 6 6.7 dual bios ....................................................................................................................... 6 6.8 hardware data protection .............................................................................................. 6 6.9 write operation status ................................................................................................... 7 7. table of operating modes ............................................................................................ 10 7.1 operating mode selection - programmer mode ........................................................... 10 7.2 operating mode selection - lpc mode ........................................................................ 10 7.3 standard lpc memory cycle definition ....................................................................... 10 8. table of command definition ....................................................................................... 11 8.1 embedded programming algorithm ............................................................................. 12 8.2 embedded erase algorithm .......................................................................................... 13 8.3 embedded #data polling algorithm .............................................................................. 14 8.4 embedded toggle bit algorithm ................................................................................... 15 8.5 software product identification and boot bl ock lockout detection acquisition flow .. 16 9. dc characteristics .......................................................................................................... 17 9.1 absolute maximum ratings .......................................................................................... 17 9.2 programmer interface mode dc operating characteristics ......................................... 17 9.3 lpc interface mode dc operating characteristics ...................................................... 18 9.4 power-up timing ........................................................................................................... 18 10. capacitance ......................................................................................................................... 18 11. programmer interface mode ac characteristics ............................................. 19
W39V080A - 2 - 11.1 ac test conditions ....................................................................................................... 19 11.2 ac test load and waveform ....................................................................................... 19 11.3 read cycle timing parameters .................................................................................... 20 11.4 write cycle timing parameters .................................................................................... 20 11.5 data polling and toggle bit timing parameters .......................................................... 20 12. timing waveforms for programmer interface mode ....................................... 21 12.1 read cycle timing diagram ......................................................................................... 21 12.2 write cycle timing diagram ......................................................................................... 21 12.3 program cycle timing diagram ................................................................................... 22 12.4 #data polling timing diagram .................................................................................... 22 12.5 toggle bit timing diagram ........................................................................................... 23 12.6 sector erase timing diagram ...................................................................................... 23 13. lpc interface mode ac characteristics ................................................................. 24 13.1 ac test conditions ....................................................................................................... 24 13.2 read/write cycle timing parameters .......................................................................... 24 13.3 reset timing parameters ............................................................................................. 24 14. timing waveforms for lpc interface mode ........................................................... 25 14.1 read cycle timing diagram ......................................................................................... 25 14.2 write cycle timing diagram ......................................................................................... 25 14.3 program cycle timing diagram ................................................................................... 26 14.4 #data polling timing diagram .................................................................................... 27 14.5 toggle bit timing diagram ........................................................................................... 28 14.6 sector erase timing diagram ...................................................................................... 29 14.7 gpi register/product id readout timing diagram ...................................................... 30 14.8 reset timing diagram .................................................................................................. 30 15. ordering information .................................................................................................... 31 16. how to read the top marking ...................................................................................... 31 17. package dimensions ......................................................................................................... 32 17.1 32l plcc ..................................................................................................................... 32 17.2 32l stsop (8x14mm) ................................................................................................. 32 17.3 40l tsop (10 mm x 20 mm) ........................................................................................ 33 18. version history ................................................................................................................. 34
W39V080A publication release date: dec. 28, 2005 - 3 - revision a4 1. general description the W39V080A is an 8-megabit, 3.3-volt onl y cmos flash memory organized as 1m 8 bits. for flexible erase capability, the 8mbits of data are divided into 16 uniform sectors of 64 kbytes. the device can be programmed and erased in-system with a standard 3.3v power supply. a 12-volt vpp is required for accelerated program. the unique cell architecture of the W39V080A results in fast program/erase operations with extremely low curr ent consumption. this device can operate at two modes, programmer bus interface mode and lpc bus interface mode. as in the programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. but in the lpc interface mode, this device complies with the in tel lpc specification. the device can also be programmed and erased using standard eprom programmers. 2. features y single 3.3-volt operations: ? 3.3-volt read ? 3.3-volt erase ? 3.3-volt program y fast program operation: ? vpp = 12v ? byte-by-byte programming: 9 s (typ.) y fast erase operation: ? sector erase 0.9 sec. (tpy.) y fast read access time: tkq 11 ns y endurance: 30k cycles (typ.) y twenty-year data retention y 16 even sectors with 64k bytes y any individual sector can be erased y dual bios function ? full-chip partition with 8m-bit or dual-block partition with 4m-bit y hardware protection: ? #tbl supports 64-kbyte boot block hardware protection ? #wp supports the whole chip except boot block hardware protection y ready/#busy output (ry/#by) ? detect program or erase cycle completion y hardware reset pin (#reset) ? reset the internal state machine to the read mode y vpp input pin ? acceleration (acc) function accelerates program timing y low power consumption ? read active current: 15 ma (typ. for lpc mode) y automatic program and erase timing with internal v pp generation y end of program or erase detection ? toggle bit ? data polling y latched address and data y ttl compatible i/o y available packages: 32l plcc, 32l stsop, 40l tsop(10 x 20 mm), 32l plcc lead free, 32l stsop lead free and 40l tsop (10 x 20 mm) lead free
W39V080A - 4 - 3. pin configurations 4. block diagram #we(#lframe) dq4(rsv) dq3(lad3) dq7(u/#l) dq6(d/#f) #oe(#init) dq5(rsv) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 32l stsop 24 23 22 21 20 19 18 17 a3(id3) mode r/#c(clk) nc v dd a10(gpi4) vpp a9(gpi3) a8(gpi2) #reset a7(gpi1) a6(gpi0) a2(id2) a1(id1) a0(id0) dq2(lad2) dq1(lad1) dq0(lad0) a5(#wp) a4(#tbl) v ss v ss ry/#by(rsv) nc nc a 1 0 ^ g p i 4 v 5 6 7 9 10 11 12 13 29 28 27 26 25 24 23 22 21 303132 12 3 4 8 201918171615 14 d q 1 ^ l a d 1 v v s s d q 6 ^ d / # v # r e s e t v d d r / # c ^ c l k v a 9 ^ g p i 3 v 32l plcc dq0(lad0) a7(gpi1) a6(gpi0) a4(#tbl) a3(id3) a2(id2) a1(id1) a0(id0) a5(#wp) mode dq7(u/#l) #we(#lframe) #oe(#init) nc a 8 ^ g p i 2 v d q 2 ^ l a d 2 v d q 3 ^ l a d 3 v d q 4 ^ r s v v d q 5 ^ r s v v v ss ry/#by(rsv) v dd nc v p p f #we(#lframe ) dq3(lad3) dq2(lad2) dq1(lad1) dq0(lad0) 1 40l tsop 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vpp vdd clk a9(gpi3) a8(gpi2) nc vss vss vdd dq7(u/#l) dq6(d/#f) vdd vss nc mode a4(#tbl) a5(#wp) 2 3 4 5 6 7 24 21 22 23 nc nc nc a10(gpi4) nc #reset nc nc a7(gpi1) a6(gpi0) dq5(rsv) dq4(rsv) a0(id0) a1(id1) a2(id2) a3(id3) ry/#by(rsv) #oe(#init) 9 10 11 12 13 14 15 16 8 17 18 19 20 0fffff lad[3:0] program- mer interface 000000 020000 01ffff 010000 00ffff #reset mode a[10:0] dq[7:0] #oe #we r/#c lpc interface clk #lframe 0f0000 0effff 64k bytes block 0 030000 02ffff #init #wp #tbl 0e0000 0dffff 0d0000 0cffff 64k bytes block 1 64k bytes block 2 64k bytes block 13 64k bytes block 14 64k bytes block 15 ry/#by 5. pin description interface sym. pgm lpc pin name mode * * interface mode selection #reset * * reset #init * initialize #tbl * top boot block lock #wp * write protect clk * clk input gpi[4:0] * general purpose inputs id[3:0] * identification inputs pull down with internal resistors lad[3:0] * address/data inputs #lframe * lpc cycle initial d/#f * dual bios/full chip pull down with internal resistors u/#l * upper 4m/lower 4m pull down with internal resistors r/#c * row/column select a[10:0] * address inputs dq[7:0] * data inputs/outputs #oe * output enable #we * write enable ry/#by * ready/busy vdd * * power supply vss * * ground rsv * * reserve pins nc * * no connection
W39V080A publication release date: dec. 28, 2005 - 5 - revision a4 6. functional description 6.1 interface mode selection and description this device can be operated in two interface m odes, one is programmer interface mode, and the other is lpc interface mode. the mode pin of the device provides the control between these two interface modes. these interface modes need to be configured before power up or return from #reset . when mode pin is set to high position, the device is in the programmer mode; while the mode pin is set to low position, it is in the lp c mode. in programmer mode, this device just behaves like traditional flash parts with 8 data lines. but the row and column address inputs are multiplexed. the row address is mapped to the higher internal address a[19:11]. and the column address is mapped to the lower internal address a[10:0]. for lpc mode, it complies with the lpc interface specification revision 1.1 through the lad[3:0] and #lframe to communicate with the system chipset . 6.2 read (write) mode in programmer interface mode, the read(write) operation of the W39V080A is controlled by #oe (#we). the #oe (#we) is held low for the host to obtain (write) data from (to) the outputs(inputs). #oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when #oe is high. as in the lp c interface the ?bit 1 of cycle type+dir? determines mode, the read or write. refer to the timing waveforms for further details. 6.3 reset operation the #reset input pin can be used in some applicat ion. when #reset pin is at high state, the device is in normal operation mode. when #reset pin is at low state, it will halt the device and all outputs will be at high impedance state. as the high state re-asserted to the #reset pin, the device will return to read or standby mode, it depends on the control signals. 6.4 boot block operation and hardware protection at initial- #tbl & #wp there is a hardware method to protect the top boot block and other sectors. before power on programmer, tie the #tbl pin to low state and t hen the top boot block will not be programmed/erased. if #wp pin is tied to low state before power on, the other sectors will not be programmed/erased. in order to detect whether the boot block featur e is set on or not, users can perform software command sequence: enter the product ident ification mode (see command codes for identification/boot block lockout detection for specific code), and then read from address ffff2(hex). you can check the dq 2/dq3 at the address ffff2 to see whether the #tbl/#wp pin is in low or high state. if the dq2 is ?0?, it means the #tbl pin is tied to high state. in such condition, whether boot block can be programmed/erased or not will depend on software setting. on the other hand, if the dq2 is ?1?, it means the #tbl pin is tied to low state, then boot block is locked no matter how the software is set. like the dq2, the dq3 invers ely mirrors the #wp state. if the dq3 is ?0?, it means the #wp pin is in high state, then a ll the sectors except the boot block can be programmed/erased. on the other hand, if the dq3 is ?1?, then all the sector s except the boot block are programmed/erased inhibited. to return to normal operation, perform a three- byte command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot blo ck lockout detection.
W39V080A - 6 - 6.5 sector erase command sector erase is a six-bus cycles operation. there ar e two "unlock" write cycles , followed by writing the "set-up" command. two more "unlo ck" write cycles then follows by the sector erase command. the sector address (any address location within the des ired sector) is latched on the rising edge of r/#c in programmer mode, while the command (30h) is latched on the rising edge of #we. sector erase does not require the user to program the device prior to erase. when erasing a sector, the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the automatic sector erase begins after the eras e command is completed, right from the rising edge of the #we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is "1" at which time the device retu rns to the read mode. data polling must be performed at an address within any of the sectors being erased. refer to the erase command flow chart using typical command strings and bus operations. 6.6 program operation the W39V080A is programmed on a byte-by-byte basis. program operation can only change logical data "1" to logical data "0." the erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. the program operation is initiated by a 4-by te command cycle (see command codes for byte programming). the device will internally enter t he program operation immediately after the byte- program command is entered. the internal pr ogram timer will automatically time-out (9 s typ. - t bp ) once it is completed and then return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle. 6.7 dual bios the W39V080A provides a solution for dual-bios app lication. in lpc mode, when d/#f is low, the device functions as a full-chip partition of 8m -bit which address ranges from fffffh to 00000h with a[19:0]. if d/#f is driven high, the device functions as a dual-block partition that each block consists of 4m-bit. for dual-block partition, there is only one 4m-bit block, either upper or lower, can be accessed. the u/#l pin selects either upper or lower 4m-bit block and its address ranges from 7ffffh to 00000h with a[19:0]. when u/#l is low, t he lower 4m-bit block will be selected; while, u/#l is high, the upper 4m-bit block will be selected. 6.8 hardware data protection the integrity of the data stored in the W39V080A is also hardware protected in the following ways: (1) noise/glitch protection: a #we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming and read operation are inhibited when v dd is less than 2.0v typical. (3) write inhibit mode: forcing #oe low or #we hi gh will inhibit the write operation. this prevents inadvertent writes during pow er-up or power-down periods.
W39V080A publication release date: dec. 28, 2005 - 7 - revision a4 6.9 write operation status the device provides several bits to determine the st atus of a program or er ase operation: dq5, dq6, and dq7. each of dq7 and dq6 provides a met hod for determining whether a program or erase operation is complete or in progress. the devic e also offers a hardware-based output signal, ry/#by in programmer mode, to determine whether an em bedded program or erase operation is in progress or has been completed. dq7: #data polling the #data polling bit, dq7, indicates whether an embedded program or erase algorithm is in progress or completed. data polling is valid a fter the rising edge of the final #we pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 and the complement of the data programmed to dq7. once the embedded program al gorithm has completed, the device outputs the data programmed to dq7. the system must prov ide the program address to read valid status information on dq7. if a program address falls with in a protected sector, #data polling on dq7 is active for about 1 s, and then the device returns to the read mode. during the embedded erase algorithm, #data po lling produces ?0? on dq7. once the embedded erase algorithm has completed, #data polling produc es ?1? on dq7. an address within any of the sectors selected for erasure must be provided to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasi ng are protected, #data polling on dq7 is active for about 100 s, and t hen the device returns to the read mode. i f not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just before the completion of an embedded pr ogram or erase operation, dq7 may change asynchronously with dq0-dq6 while output enable (#oe) is set to low. that is, the device may change from providing status information to va lid data on dq7. depending on when it samples the dq7 output, the system may read the status or va lid data. even if the dev ice has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq6 may be still invalid. valid data on dq7-dq0 will appear on successive read cycles. ry/#by: ready/#busy the ry/#by is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/#by status is valid after the rising edge of the final #we pulse in the command sequence. since ry/#by is an open-drain out put, several ry/#by pins can be tied together in parallel with a pull-up resistor to vdd. when the output is low (busy), the device is active ly erasing or programming. when the output is high (ready), the device is in t he read mode or standby mode. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded progr am or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final #we pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operat ion, successive read cycles to any address cause dq6 to toggle. the system may use either #oe to control the read cycles. once the operation has completed, dq6 stops toggling.
W39V080A - 8 - after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for about 100 s, and then returns to readi ng array data. if not all selected sectors are protected, the embedded erase algorithm erases t he unprotected sectors, and ignores the selected sectors which are protected. the system can use dq6 to determine whether a sector is actively erasing. if the device is actively erasing (i.e., the embedded erase algorithm is in progress), dq6 toggles. if a program address falls within a protected sector, dq6 toggles for about 1 s after the program command sequence is written, and then returns to reading array data. reading toggle bits dq6 whenever the system initially starts to read toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bit is toggling or not. typically, the system would note and store the value of the toggle bit after the first read. while after the second read, the system would compare the new value of the toggle bit with the first one. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7-dq0 on the following read cycle. however, if after the initial two read cycles, the sy stem finds that the toggle bit is still toggling, the system also should note whether t he value of dq5 is high or not(see the section on dq5). if dq5 is high, the system should then determi ne again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase oper ation. if it is still togg ling, the device did not completed the operation, and the sy stem must write the reset command to return to reading array data. then the system initially determines that the toggle bit is togg ling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, and determines the status as described in the previous paragraph. alter natively, the system may choose to perform other system tasks. in this case, the system must start at t he beginning of the algorithm while it returns to determine the status of the operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. dq5 produces ?1? under these conditions which indica tes that the program or erase cycle was not successfully completed. the device may output ?1? on dq5 if t he system tries to program ?1? to a location that was previously programmed to ?0.? only the erase operation can change ?0? back to ?1.? under this condition, the device stops the operation, and while the timi ng limit has been exceeded, dq5 produces ?1.? under both these conditions, the system must hardware reset to return to the read mode. register there are two kinds of registers on this device, the general purpose input registers and product identification registers. users can access these registers thr ough respective address in the 4gbytes memory map. there are detail descriptions in the sections below. general purpose inputs register this register reads the gpi[4:0] pins on the w39v 080a.this is a pass-through register which can read via memory address ffbc0100(hex), or ffbxe100(hex). since it is pa ss-through register, there is no default value.
W39V080A publication release date: dec. 28, 2005 - 9 - revision a4 gpi register table bit function 7 ? 5 reserved 4 read gpi4 pin status 3 read gpi3 pin status 2 read gpi2 pin status 1 read gpi1 pin status 0 read gpi0 pin status product identification registers there is a software method to read out the product identification in both the programmer interface mode and the lpc interface mode. thus, the progr amming equipment can automatically matches the device with its proper erase and programming algorithms. in the full-chip(8mb) lpc interface mode, a r ead from ffbc, 0000(hex) can output the manufacturer code, da(hex). a read from ffbc, 0001(hex ) can output the device code d0(hex). for dual-bios(4mbx2) lpc mode , a read from ffb c, 0000(hex) can output t he manufacturer code, da(hex). a read from ffbc,0001(hex) can output the device code 90(hex). in the software access mode, a jedec 3-by te command sequence can be used to access the product id for programmer interface mode. a r ead from address 0000(hex) outputs the manufacturer code, da(hex). a read from address 0001(hex) outputs sequence or an alternate one-byte command sequence (see command definition table for detail) .the device code, d0(hex).? the product id operation can be terminated by a three-byte command. identification input pins id[3:0] these pins are part of mechanism that allows mu ltiple parts to be used on the same bus. the boot device should be 0000b. and all the subsequent parts should use the up-count strapping. memory address map there are 8m bytes space reserved for bios addr essing. the 8m bytes are mapped into a single 4m system address by dividing the roms into two 4m byte pages. for accessing the 4m byte bios storage space, the id[2:1] pins are inverted in the rom and are compared to address lines [21:20]. id[3] can be used as like active low chip-select pin. the 32mbit address space is as below: block lock address range 4m byte bios rom none ffff, ffffh: ffc0, 0000h the rom responds to top 1m byte pages based on t he id pins strapping according to the following table: id[2:1] pins rom based address range 00x ffff, ffffh: fff0, 0000h 01x ffef, ffffh: fef0, 0000h 10x ffdf, ffffh: ffd0, 0000h 11x ffcf, ffffh: ffc0, 0000h
W39V080A - 10 - 7. table of operating modes 7.1 operating mode selection - programmer mode mode pins #oe #we #reset address dq. read v il v ih v ih ain dout write v ih v il v ih ain din standby x x v il x high z write inhibit v il x v ih x high z/dout x v ih v ih x high z/dout output disable v ih x v ih x high z 7.2 operating mode selection - lpc mode operation modes in lpc interface mode are determined by "cycle type" when it is selected. when it is not selected, its outputs (lad[3:0]) will be dis able. please reference to the "standard lpc memory cycle definition". 7.3 standard lpc memory cycle definition field no. of clocks description start 1 "0000b" appears on lpc bus to indicate the initial cycle type & dir 1 "010xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "x" mean don't have to care. tar 2 turned around time addr. 8 address phase for memory cycle. lpc supports the 32 bits address protocol. the addresses transfer most significant nibble first and least significant nibble last. (i.e. a ddress[31:28] on lad[3:0] first , and address[3:0] on lad[3:0] last.) sync. n synchronous to add wait state. "0000b" means ready, "0101b" means short wait, "0110b" means long wait, "1001b" for dma only, "1010b" means error, other values are reserved. data 2 data phase for memory cycle. the data transfer least significant nibble first and most significant nibble last. (i.e. dq[3:0] on lad[3:0] first , then dq[7:4] on lad[3:0] last.)
W39V080A publication release date: dec. 28, 2005 - 11 - revision a4 8. table of command definition command no. of 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle description cycles (1) addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (5) 30 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (4) 3 5555 aa 2aaa 55 5555 f0 product id exit (4) 1 xxxx f0 notes: 1. the cycle means the write command cycle not the lpc clock cycle. 2. the column address / row address are mapped to the low / high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[7:0] are mapped to the internal a[19:11] 3. address format: a14 ? a0 (hex); data format: dq7-dq0 (hex) 4. either one of the two product id exit commands can be used. 5. sa: sector address sa = fxxxxh for unique sector15 (boot sector) sa = 7xxxxh for unique sector7 sa = exxxxh for unique sector14 sa = 6xxxxh for unique sector6 sa = dxxxxh for unique sector13 sa = 5xxxxh for unique sector5 sa = cxxxxh for unique sector12 sa = 4xxxxh for unique sector4 sa = bxxxxh for unique sector11 sa = 3xxxxh for unique sector3 sa = axxxxh for unique sector10 sa = 2xxxxh for unique sector2 sa = 9xxxxh for unique sector9 sa = 1xxxxh for unique sector1 sa = 8xxxxh for unique sector8 sa = 0xxxxh for unique sector0
W39V080A - 12 - 8.1 embedded programming algorithm start write program command sequence (see below) programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit program command sequence (address/command):
W39V080A publication release date: dec. 28, 2005 - 13 - revision a4 8.2 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h sector address/30h (address/command): individual sector erase command sequence
W39V080A - 14 - 8.3 embedded #data polling algorithm start read byte (dq0 - dq7) address = sa pass dq7 = data ? yes fail dq5 = 1 no read byte (dq0 - dq7) address = sa dq7 = data yes no yes no note:sa = valid address for programming .during a sector erase operation, a valid address is an addr ess within any sector selected for erasure.
W39V080A publication release date: dec. 28, 2005 - 15 - revision a4 8.4 embedded toggle bit algorithm yes no pass read byte (dq0-dq7) start read byte (dq0-dq7) dq5 = 1 ? read byte (dq0-dq7) twin toggle bit =toggle ? toggle bit =toggle ? fail no yes no note: recheck toggle bit because it may st op toggling as dq5 changes to ?1? .
W39V080A - 16 - 8.5 software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 00000 data = da read address = 00001 data = d0 read address =ffff2 check dq[3:0] of data outputs (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s notes for software product identificati on/boot block lockout detection: (1) data format: dq7? dq0 (hex); address format: a14 ? a0 (hex) (2) a1? a19 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) the dq[3:2] to indicate the sectors protect status as below: dq2 dq3 0 64kbytes boot block unlocked by #tbl hardware trapping whole chip unlocked by #wp hardware trapping except boot block 1 64kbytes boot block locked by #tbl hardware trapping whole chip locked by #wp hardware trapping except boot block (5) the device returns to standard operation mode. (6) optional 1-write cycle (write f0 (hex.) at xxxx address) c an be used to exit the product identification/boot block lockout detection.
W39V080A publication release date: dec. 28, 2005 - 17 - revision a4 9. dc characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage to v ss potential -0.5 to +4.0 v operating temperature 0 to +70 c storage temperature -65 to +150 c d.c. voltage on any pin to ground potential -0.5 to v dd +0.5 v v pp voltage -0.5 to +13 v transient voltage (<20 ns) on any pin to ground potential -1.0 to v dd +0.5 v note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 9.2 programmer interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current (read) icc1 in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 15 20 ma power supply current (erase/ write) icc2 in read or write mode, all dqs open address inputs = 3.0v/0v, at f = 3 mhz - 35 45 ma input leakage current ili vin = vss to vdd - - 90 a output leakage current ilo vout = vss to vdd - - 90 a input low voltage vil - -0.5 - 0.8 v input high voltage vih - 2.0 - vdd +0.5 v output low voltage vol iol = 2.1 ma - - 0.45 v output high voltage voh ioh = -0.1ma 2.4 - - v
W39V080A - 18 - 9.3 lpc interface mode dc operating characteristics (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current (read) i cc1 all i out = 0a, clk = 33 mhz, in lpc mode operation. - 15 20 ma power supply current (erase/write) i cc2 all i out = 0a, clk = 33 mhz, in lpc mode operation. - 35 45 ma standby current 1 isb1 #lframe = 0.9 v dd , clk = 33 mhz, all inputs = 0.9 v dd / 0.1 v dd no internal operation - 20 50 ua standby current 2 isb2 #lframe = 0.1 v dd , clk = 33 mhz, all inputs = 0.9 v dd /0.1 v dd no internal operation. - 3 10 ma input low voltage v il - -0.5 - 0.3 v dd v input low voltage of #init v ili - -0.5 - 0.2 v dd v input high voltage v ih - 0.5 v dd - v dd +0.5 v input high voltage of #init pin v ihi - 1.35 v - v dd +0.5 v output low voltage v ol i ol = 1.5 ma - - 0.1 v dd v output high voltage v oh i oh = -0.5 ma 0.9 v dd - - v 9.4 power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms 10. capacitance (v dd = 3.3v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf
W39V080A publication release date: dec. 28, 2005 - 19 - revision a4 11. programmer interface mode ac characteristics 11.1 ac test conditions parameter conditions input pulse levels 0v to 0.9 v dd input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf 11.2 ac test load and waveform +3.3v 1.8k 1.3k d out 30 pf (including jig and scope) input 0.9vdd 0v test point test point 1.5v 1.5v output
W39V080A - 20 - programmer interface mode ac characteristics, continued 11.3 read cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) W39V080A parameter symbol min. max. unit read cycle time t rc 350 - ns row / column address set up time t as 50 - ns row / column address hold time t ah 50 - ns address access time t aa - 200 ns output enable access time t oe - 75 ns #oe low to active output t olz 0 - ns #oe high to high-z output t ohz - 35 ns output hold from address change t oh 0 - ns 11.4 write cycle timing parameters parameter symbol min. typ. max. unit reset time t rst 1 - - s address setup time t as 50 - - ns address hold time t ah 50 - - ns r/#c to write enable high time t cwh 50 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 50 - - ns #oe hold time t oeh 0 - - ns byte programming time t bp - 9 250 s sector erase cycle time (note (c)) t pec - 0.9 6 s program/erase valid to ry/#by delay t busy 90 - - ns note: all ac timing signals observe the following guideli nes for determining setup and hold times: (a) high level signal's refer ence level is input high and (b) low level signal's reference level is input low. ref. to the ac testing condition. (c) exclude 00h pre-program prior to erasure. (in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure 11.5 data polling and toggle bit timing parameters W39V080A parameter symbol min. max. unit #oe to data polling output delay t oep - 40 ns #oe to toggle bit output delay t oet - 40 ns toggle or polling interval --- 50 - ms
W39V080A publication release date: dec. 28, 2005 - 21 - revision a4 12. timing waveforms for programmer interface mode 12.1 read cycle timing diagram dq[7:0] high-z #oe #we v ih t oh t aa data valid t ohz high-z t olz t oe #reset a[10:0] t rc #c r/ t as t ah row address column address t as t ah column address row address t rst 12.2 write cycle timing diagram data valid t cwh t oeh t wp t ds t as t ah t wph t dh dq[7:0] #oe #we #c r/ #reset a[10:0] column address row address t rst t as t ah
W39V080A - 22 - timing waveforms for programmer interface mode, continued 12.3 program cycle timing diagram a[10:0] byte 0 byte 1 byte 2 internal write start dq[7:0] #oe #we byte program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 programmed address data-in byte 3 note: the internal address a[19:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[8:0] are mapped to the internal a[19:11]. #cr/ (internal a[19:0]) t busy ry/#by 12.4 #data polling timing diagram a[10:0] dq7 #we #oe x x x t oep t bp #cr/ x (internal a[19:0]) an an an an ry/#by t busy
W39V080A publication release date: dec. 28, 2005 - 23 - revision a4 timing waveforms for programmer interface mode, continued 12.5 toggle bit timing diagram a[10:0] dq6 #we #oe t oet t bp #cr/ ry/#by 12.6 sector erase timing diagram sb2 sb1 sb0 a[10:0] dq[7:0] #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 3.3v-only sector erase t wp t wph t pec 5555 2aaa 5555 5555 2aaa sa aa 55 80 aa 55 30 sa = sector address, please ref. to the "table of command definition" note: the internal address a[19:0] are converted from external column/row address. column/row address are mapped to the low/high order internal address. i.e. column address a[10:0] are mapped to the internal a[10:0], row address a[8:0] are mapped to the internal a[19:11]. #cr/ (internal a[19:0]) t busy ry/#by
W39V080A - 24 - 13. lpc interface mode ac characteristics 13.1 ac test conditions parameter conditions input pulse levels 0.6 v dd to 0.2 v dd input rise/fall slew rate 1 v/ns input/output timing level 0.4v dd / 0.4v dd output load 1 ttl gate and c l = 10 pf 13.2 read/write cycle timing parameters (v dd = 3.3v 0.3v, v ss = 0v, t a = 0 to 70 c) W39V080A parameter symbol min. max. unit clock cycle time t cyc 30 - ns input set up time t su 7 - ns input hold time t hd 0 - ns clock to data valid t kq 2 11 ns note: minimum and maximum time have different load. please refer to pci specification. 13.3 reset timing parameters parameter symbol min. typ. max. unit v dd stable to reset active t prst 1 - - ms clock stable to reset active t krst 100 - - s reset pulse width t rstp 100 - - ns reset active to output float t rstf - - 50 ns reset inactive to input active t rst 10 - - s note: all ac timing signals observe the following guideli nes for determining setup and hold times: (a) high level signal's refer ence level is input high and (b) low level signal's reference level is input low. please refer to the ac testing condition.
W39V080A publication release date: dec. 28, 2005 - 25 - revision a4 14. timing waveforms for lpc interface mode 14.1 read cycle timing diagram t cyc lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next star t 1 clock 2 clocks 1 clock 010xb 0000b a[15:12] address sync tar 1111b tri-state 0000b t kq t hd t su a[11:8] a[7:4] a[3:0] data out 2 clocks d[7:4] data d[3:0] 0000b a[19:16] a[31:28] a[23:20] a[27:24] #lframe #reset 14.2 write cycle timing diagram t cyc lad[3:0] start memory write cycle load address in 8 clocks clk 1 clock 1 clock tar next star t 1 clock 2 clocks 1 clock 011xb 0000b a[15:12] load data in 2 clocks d[7:4] address sync tar data 1111b tri-state 0000b t hd t su a[11:8] a[7:4] a[3:0] d[3:0] 0000b a[19:16] a[31:28] a[23:20] a[27:24] #lframe #reset
W39V080A - 26 - timing waveforms, for lpc interface mode, continued 14.3 program cycle timing diagram lad[3:0] 1st start memory write cycle load address "5555" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "a0" in 2 clocks 1010b 0000b write the 3rd command to the device in lpc mode. 4th start load ain in 8 clocks clk clk clk 1 clock 1 clock tar sync internal program start tar 1 clock 2 clocks 011xb 0000b a[15:12] load din in 2 clocks d[7:4] write the 4th command(target location to be programmed) to the device in lpc mode. a[11:8] a[7:4] a[3:0] d[3:0] 1111b tri-state 0000b data address address address address sync tar data sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b memory write cycle memory write cycle memory write cycle internal program start a[19:16] a[31:28] a[23:20] a[27:24] lad[3:0] lad[3:0] lad[3:0] #lframe #reset #lframe #reset #lframe #reset #lframe #reset
W39V080A publication release date: dec. 28, 2005 - 27 - revision a4 timing waveforms for lpc interface mode, continued 14.4 #data polling timing diagram read the dq7 to see if the internal write complete or not. start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb an[19:16] an[15:12] address sync tar 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] data out 2 clocks dn7,xxx data xxxxb 0000b start memory read cycle load address in 8 clocks clk 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b address sync tar 1111b tri-state 0000b data out 2 clocks data 0000b when internal write complete, the dq7 will equal to dn7. dn7,xxx xxxxb an[15:12] an[11:8] an[7:4] an[3:0] lad[3:0] 1st start load address "an" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in lpc mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] memory write cycle 0000b 1 clock a[19:16] a[31:28] a[23:20] a[27:24] an[31:28] an[27:24] an[23:20] an[19:16] lad[3:0] lad[3:0] #lframe #reset #lframe #reset #lframe #reset
W39V080A - 28 - timing waveforms for lpc interface mode, continued 14.5 toggle bit timing diagram read the dq6 to see if the internal write complete or not. lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb address sync tar 1111b tri-state 0000b data out 2 clocks x,d6,xxb data xxxxb 0000b lad[3:0] start memory read cycle load address in 8 clocks clk 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b xxxxb xxxxb xxxxb address sync tar 1111b tri-state 0000b data out 2 clocks data 0000b when internal write complete, the dq6 will stop toggle. x,d6,xxb xxxxb lad[3:0] 1st start load address "an" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb an[15:12] load data "dn" in 2 clocks dn[7:4] write the last command(program or erase) to the device in lpc mode. address sync tar data 1111b tri-state 0000b an[11:8] an[7:4] an[3:0] dn[3:0] an[19:16] memory write cycle xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb xxxxb 1 clock #lframe #reset #lframe #reset #lframe #reset
W39V080A publication release date: dec. 28, 2005 - 29 - revision a4 timing waveforms for lpc interface mode, continued 14.6 sector erase timing diagram 6th start load sector address in 8 clocks 1 clock 1 clock tar sync internal erase start tar 1 clock 2 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb sa[19:16] load data "30" in 2 clocks 0011b write the 6th command(target sector to be erased) to the device in lpc mode. 0000b 1111b tri-state 0000b data address 1st start load address "5555" in 8 clocks clk 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 1st command to the device in lpc mode. clk clk clk address sync tar data 2nd start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 2nd command to the device in lpc mode. 3rd start load address "5555" in 8 clocks 1 clocks 1 clocks tar start next command 1 clocks 2 clocks 1 clocks 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "80" in 2 clocks 1000b 0000b write the 3rd command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b 1111b tri-state 0000b 4th start memory write cycle load address "5555" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x101b 0101b 0101b 0101b load data "aa" in 2 clocks 1010b 1010b write the 4th command to the device in lpc mode. 5th start load address "2aaa" in 8 clocks 1 clock 1 clock tar start next command 1 clock 2 clocks 1 clock 011xb 0000b xxxxb xxxxb xxxxb xxxxb x010b 1010b 1010b 1010b load data "55" in 2 clocks 0101b 0101b write the 5th command to the device in lpc mode. address address sync tar data sync tar data 1111b tri-state 0000b 1111b tri-state 0000b clk clk xxxxb xxxxb xxxxb memory write cycle memory write cycle memory write cycle memory write cycle memory write cycle internal erase start lad[3:0] lad[3:0] lad[3:0] lad[3:0] lad[3:0] lad[3:0] #lframe #reset #lframe #reset #lframe #reset #lframe #reset #lframe #reset #lframe #reset
W39V080A - 30 - timing waveforms for lpc interface mode, continued 14.7 gpi register/product id readout timing diagram note: read the dq[4:0] to capture the states(high or low) of the gpi[4:0] input pins. the dq[7:5] are reserved lad[3:0] start memory read cycle load address "ffbc0100(hex), or ffbxe100(hex)" in 8 clocks clk 1 clock 1 clock tar next start 1 clock 2 clocks 1 clock 010xb 0000b 1111b address sync tar 1111b tri-state 0000b data out 2 clocks d[7:4] data 0000b 1111b 1011b xxxxb 1110b 0001b 0000b 0000b d[3:0] #lframe #reset 14.8 reset timing diagram clk vdd lad[3:0] t prst t krst t rstp t rst f t rst #lframe #reset
W39V080A publication release date: dec. 28, 2005 - 31 - revision a4 15. ordering information part no. access time (ns) power supply current max. (ma) standby vdd current max. (ua) package W39V080Ap 11 15 20 32l plcc W39V080Aq 11 15 20 32l stsop W39V080At 11 15 20 40l tsop W39V080Apz 11 15 20 32l plcc lead free W39V080Aqz 11 15 20 32l stsop lead free W39V080Atz 11 15 20 40l tsop lead free notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 16. how to read the top marking example: the top marking of 32-pin stsop W39V080Aq W39V080Aq 2138977a-a12 149obsa 1 st line: winbond logo 2 nd line: the part number: W39V080Aq 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in ?01, week 49 o: assembly house id : a means ase, o means ose, ...etc. b: ic revision; a means version a, b means version b, ...etc. sa: process code
W39V080A - 32 - 17. package dimensions 17.1 32l plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusio 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 17.2 32l stsop (8x14mm) min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm a a a 2 1 l l 1 y e h d d c b e
W39V080A publication release date: dec. 28, 2005 - 33 - revision a4 package dimensions, continued 17.3 40l tsop (10 mm x 20 mm)
W39V080A - 34 - 18. version history version date page description a1 jan. 5, 2005 - initial issued a2 april 14, 2005 34 add important notice a3 oct. 3, 2005 3 revise endurance 10k cycles to 30k cycles revise page8 dq5: exceeded timing limits description, page15 embedded toggle bit algorithm and page4 pin configuration (a0 to a3) a4 dec. 28, 2005 4,8,15 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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